The operating speed of semiconductor device decreases as the product RC (time constant) of wiring resistance (R) and parasitic capacitance (c) between wirings increases, and the parasitic capacitance (C) between wirings increases inversely proportional to the interval of wirings. Therefore, in order to enhance the operating speed of semiconductor device, it is important that the parasitic capacitance is reduced.
The parasitic capacitance between different layers can be reduced by increasing the thickness of interlayer dielectric film. On the other hand, in order to reduce the parasitic capacitance between same layers, any one of the ways to increase the wiring interval, to reduce the wiring height and to use a low-specific-permittivity interlayer insulating film is necessary of them, the ways to increase the wiring interval and to reduce the wiring height are not suitable since they go against the recent trends that, with the micro-structuring of semiconductor device, the wiring interval is decreased and the aspect ratio between wirings (wiring thickness(=wiring height)/interval of wirings) is increased. So, for wirings of same layers, it is necessary to reduce the parasitic capacitance by filling the low-specific-permittivity interlayer insulating film. Especially for part with narrow wiring interval and part with high aspect ratio between wirings, since RC (time constant) is essentially high as described earlier, it is highly necessary to fill the low-specific-permittivity interlayer insulating film.
On the other, multilayer wiring has been in wide use with the micro-structuring of semiconductor device. As the interlayer dielectric film for semiconductor device with multilayer wiring, silicon-dioxide-system insulating film is used. However, when metal such as aluminum etc. is used as the wiring material, the temperature in forming the interlayer dielectric film is limited lower than 450.degree. C. So, PE-TEOS film is wide used as the interlayer dielectric film. PE-TEOS film is silicon dioxide film formed by plasma enhanced chemical vapor deposition using TEOS (tetraethylorthosilicate). The specific permittivity of PE-TEOS film is about 4.2 to 4.4. However, when buried insulating film is formed only by PE-TEOS film, there is room for improvement at points below. Namely, a wiring gap with wiring interval of shorter than 0.5 .mu.m and aspect ratio of higher than 1 cannot be completely buried, and therefore a void is likely to occur between the micro-wirings. Also, the unevenness of surface is likely to increase, which may cause an etch residue of metal in dry-etching the upper metal wiring and a disconnection of upper wiring itself.
Accordingly, the method to bury a low-specific-permittivity insulating film between the micro-wirings and to planarize the surface has been needed. Such a method is known as conventional methods described below.
The first conventional method is reported by Furusawa et al. in Symposium on VLSI Technology, 1995. This method uses an interlayer dielectric film having the sandwich structure that organic SOG (spin on glass) film with a low specific permittivity of 3.0 is sandwiched by upper and lower PE-TEOS films with specific permittivity of 4.5. Here, organic SOG film is left on the entire surface without etching-back (non-etch-back process). Thus, it has the structure that organic SOG film is exposed at the sidewall of via hole.
FIGS. 1A to 1C are cross sectional views showing in sequence the steps of the first conventional method for making a semiconductor device. First, as shown in FIG. 1A, insulating film 602 is formed on the entire surface of a silicon substrate 601, and then lower wirings 603a to 603c of metal film mainly composed of aluminum are formed using photolithography and dry etching method. On these wirings, first silicon dioxide film 604 of FE-TEOS film is thin formed as a contact layer. Further thereon, organic-contained SOG (organicSOG) film 605 with a specific permittivity of 3.0 is formed by coating-baking method. Finally, on the entire surface, second silicon dioxide film 606 of PE-TEOS film is thin formed. Thus, interlayer dielectric film 615 composed of three layers of the first silicon dioxide film 604, organic SOG film 605 and second silicon dioxide film 606 is formed.
Then, as shown in FIG. 1B, by photolithography and dry etching method, via holes 608a, 608b are formed using photoresist 607 as a mask. When photoresist 607 is removed with oxygen plasma, the following method is used. For the first step, at a low pressure of 1.2 mTorr, using oxygen reactive ion etching method, the surface of organic SOG film 605 that is exposed on the sidewall of the via holes 608a, 608b is vitrified. For the second step, at a low pressure of 1 Torr, photoresist 607 is removed ashing with oxygen. Especially this step is shown in FIG. 1B. Finally, in order to completely remove the residue of photoresist, the wet-type photoresist removal is conducted. With the above steps, the desired via holes 608a, 608b are formed in the interlayer dielectric film 615.
Finally, as shown in FIG. 1C, by sputtering method, titanium film 610 and titanium nitride film 611 are formed on the entire surface. Then, by thermal CVD (chemical vapor deposition) method, tungsten film 612 is formed.
The second conventional method is disclosed in Japanese patent application laid-open No.8-107149 (1996). In this publication, the first and third embodiments are applicable to coating-system organic-contained insulating film. FIGS. 2A to 2C are cross sectional views showing in sequence the steps of the second conventional method, which especially corresponds to the third embodiment in the publication. The difference between the first and third embodiments is just about whether first oxide upper layer 704 is formed over a metal conductor 703 or not. Both of the embodiments use interlayer dielectric film 710 having the sandwich structure composed of three layers of oxide liner 706, low-permittivity film 708 and second oxide upper layer 709. The characteristic points are that base-layer insulating film 702 is dug down when forming the metal conductor 703, and that the oxide liner 706 is formed thinner at the side of wiring than on the top of wiring Owing to these points, a sufficient amount of low-permittivity film 708 can be buried between the wirings, thereby reducing the parasitic capacitance between the wirings. This method is explained below, referring to FIGS. 2A to 2C.
First, as shown in FIG. 2A, insulating film 702 is formed on the entire surface of a silicon substrate 701, and then metal film mainly composed of aluminum-copper alloy and its upper oxide layer are formed into the first oxide upper layer 704 and metal conductor 703, using photolithography and dry etching method. In this step, insulating film 702 is dug down about 100 nm. Thereon, the oxide layer 706 of PE-TEOS film is formed. In this step, the oxide liner 706 is formed thinner at the side of wiring than on the top of wiring.
Then, as shown in FIG. 2B, low-permittivity film 707 of organic SOG is formed by coating-baking method.
Then, as shown in FIG. 2C, the low-permittivity film 707 is etched back designating time until it becomes lower than the top of the oxide liner 706, thereby forming the low-permittivity film 708 between the metal conductors. Then, the second oxide upper layer of PE-TEOS film 709 is formed on the entire surface. As a result, the interlayer dielectric film 710 composed of three layers of oxide liner 706, low-permittivity film 708 and second oxide upper layer 709.
However, in the first conventional method, as shown in FIG. 1B, when the photoresist 607 is removed ashing with oxygen plasma 609, the organic SOG film 605 exposed at the sidewall of the via holes 608a, 608b is likely to contract or retreat. When using the organic SOG film, it is necessary to increase the content of organic component so as to reduce the specific permittivity. However, when increasing the content of organic component, the component to be vitrified at the surface of the organic SOG film decreases and therefore the anti-oxygen-plasma-etching characteristic is deteriorated This is why the above phenomenon occurs.
Also, in the first conventional method, as shown in FIG. 1C, when the tungsten film 612 is formed on the entire surface, voids 613a, 613b are likely to occur in the via holes 608a, 608b. It is a defect called poisoned via. The first reason why this phenomenon occurs is that water absorbed is discharged from the organic SOG film 605 when forming the tungsten film 612. Also, the second reason is that due to the contraction or retreating of the organic SOG film 605, the titanium film 610 and titanium nitride film 611 are not formed at the sidewall of the via hole when forming them by sputtering.
The above problems in the first conventional method are further detailed below. In general, organic SOG film has silicon dioxide as amatrix, and includes an organic component such as methyl group (CH.sub.3 --). Since it includes the organic component and has a density lower than silicon dioxide film, the specific permittivity of organic SOG film is lower than that (.epsilon.=3.9) of silicon dioxide film. The permittivity of organic SOG film reduces as the content of organic component increases. Also, since the organic SOG film has the organic component, it has a hydrophobic property and it has a hygroscopic property lower than inorganic SOG film whereas it is porous. Therefore, normally, there occurs no increase in specific permittivity caused by the moisture absorption. However, as the organic component is oxidized by oxygen plasma treatment to give inorganic silicon dioxide film, it starts absorbing moisture. Thus, for organic SOG film that has a low permittivity and much organic component, when the via hole is formed in the interlayer dielectric film by photolithography and dry etching method and then the oxygen plasma ashing treatment is conducted for removing the photoresist, the organic component of organic SOG film exposed at the sidewall of the via hole is oxidized and removed. Along with the oxidation, the organic SOG film exposed at the sidewall contracts or retreats. Also, the contracted organic SOG film is inorganized nearby the via hole and starts absorbing moisture. Thereafter, when the upper wiring is formed by sputtering method, water absorbed evaporates from the organic SOG film at the via hole, expanding the volume to cause a poisoned via defect.
In the first conventional method, by vitrifying (inorganizing) the organic SOG-film exposed at the sidewall of the via hole by oxygen reactive ion etching, the occurrence of poisoned via defect is suppressed. However, to increase the content of organic component to reduce the permittivity causes a decrease for the component vitrified, therefore incurring the above problem.
Also, in the first conventional method, when the tungsten film 612 is formed on the entire surface as shown in FIG. 1C, a crack 614 is likely to occur in the interlayer dielectric film 615 since thicker organic SOG film is formed in the large-area part (part with a wide interval of wirings). This is because the organic SOG film 605, which is formed by coating-baking method, contracts every time the thermal treatment at around 400.degree. C. such as blanket tungsten growth or annealing is conducted and thereby the internal stress occurs. The planarization of the entire chip depends on the coating characteristic of the organic SOG film 605, and it is necessary to thicken the organic SOG film 605 to obtain a sufficient planarization. However, as the thickness of the organic SOG film 605 increases, the internal stress (tensile stress) also increases. When the internal stress is greater than a given value, the crack 614 occurs. This problem becomes significant especially in case of a multilayer structure.
In the second conventional method, as shown in FIG. 2C, it is difficult to obtain a sufficient planarization by the etching back method to the organic SOG film 707. This is because the over-etching is required in order to completely remove the organic SOG film 707 from the via-hole-forming region to avoid the poisoned via defect as described earlier. Namely, as the coating characteristic of organic SOG film, organic SOG film having a same thickness as a region where no metal conductor exists must be formed on the large-area metal conductor 703. To completely remove the organic SoG filmon the metal conductor causes a deterioration in planarization since the base-layer oxide liner is difficult to etch. A further reason is that the organic SOG film 707 between micro-wirings must be etched in the etching back when the oxide liner 706 is only formed thinner at the side of wiring than on the top of wiring.
Further, when applying the first and second conventional methods to the multilayer structure, it is difficult to obtain the planarization of the entire chip to form a micro-structured wiring and via hole. This is because as the coating characteristic of organic SOG film, organic SOG film having a same thickness as a region where no metal conductor exists must be formed on the large-area metal conductor. Therefore, the absolute step of the large-area metal conductor remains in situ. When the step is accumulated according as the number of wiring layers is increased two to three or more, the absolute step may exceed the focus margin for photolithography. In this case, it is impossible to form a micro-structured wiring and via hole.